Isolated synchronous rectification-type dc/dc converter

ABSTRACT

An external circuit element RSET is connected in use to an SET terminal. A synchronous rectification controller generates a pulse signal Si based on a control time determined according to the state of the SET terminal. A driver switches on and off the synchronous rectification transistor according to the pulse signal S1. An abnormal state detection circuit is capable of detecting an open-circuit state and/or a short-circuit state that can occur in the SET terminal. When the abnormal state detection circuit detects such an open-circuit state and/or short-circuit state, the abnormal state detection circuit asserts a detection signal S11. When the detection signal S11 is asserted, a primary-side controller arranged on the primary side of the DC/DC converter is instructed to suspend the switching operation of a switching transistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation application of U.S. patentapplication Ser. No. 15059445, filed on Mar. 3, 2016, the entirecontents of which is incorporated herein by reference and priority towhich is hereby claimed. Priority under 35 U.S.C. §119(a) and 35 U.S.C.§365(b) is hereby claimed from Japanese Patent Application 2015-041611filed on Mar. 3, 2015, the entire contents of which is incorporatedherein by reference.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to an insulated synchronous rectificationDC/DC converter.

Description of the Related Art

Various kinds of consumer electronics devices such as TVs,refrigerators, etc., each operate receiving commercial AC electric powerfrom an external circuit. Also, electronic devices such as laptopcomputers, cellular phone terminals, and tablet PCs are each configuredto operate using commercial AC electric power, and/or to be capable ofcharging a built-in battery using such commercial AC electric power.Such consumer electronics devices and electronic devices (which willcollectively be referred to as “electronic devices” hereafter) eachinclude a built-in power supply apparatus (AC/DC converter) thatperforms AC/DC conversion of commercial AC voltage. Alternatively, insome cases, such an AC/DC converter is built into an external powersupply adapter (AC adapter) for such an electronic device.

FIG. 1 is a block diagram showing an AC/DC converter 100 r investigatedby the present inventor. The AC/DC converter 100 r mainly includes afilter 102, a rectifier circuit 104, a smoothing capacitor 106, and aDC/DC converter 200 r.

The commercial AC voltage V_(AC) is input to the filter 102 via a fuseand an input capacitor (not shown). The filter 102 removes noiseincluded in the commercial AC voltage V_(AC). The rectifier circuit 104is configured as a diode bridge circuit which performs full-waverectification of the commercial AC voltage Vac. The output voltage ofthe rectifier circuit 104 is smoothed by the smoothing capacitor 106,thereby generating a converted DC voltage V_(IN).

An insulated DC/DC converter 200 r receives the DC voltage V_(IN) via aninput terminal P1, steps down the DC voltage V_(IN) thus received so asto generate an output voltage V_(OUT) stabilized to a target value, andsupplies the output voltage V_(OUT) thus stabilized to a load (notshown) connected between an output terminal P2 and a ground terminal P3.

The DC/DC converter 200 r includes a primary-side controller 202, aphotocoupler 204, a shunt regulator 206, an output circuit 210, asecondary-side controller 300 r, and other circuit components. Theoutput circuit 210 includes a transformer T1, a diode D1, an outputcapacitor C1, a switching transistor M1, and a synchronous rectificationtransistor M2. The output circuit 210 has the same topology as those oftypical synchronous rectification flyback converters, and accordinglydescription thereof will be omitted.

The switching transistor M1 connected to the primary winding W1 of thetransformer T1 performs switching so as to step down the input voltageV_(IN), thereby generating the output voltage V_(OUT). With such anarrangement, the primary-side controller 202 adjusts the duty ratio ofthe switching of the switching transistor M1.

The output voltage V_(OUT) of the DC/DC converter 200 r is divided bymeans of resistors R1 and R2. The cathode (K) terminal of the shuntregulator 206 is connected to a light-emitting element (light-emittingdiode) on the input side of the photocoupler 204. The anode (A) terminalof the shunt regulator 206 is grounded. The divided voltage (voltagedetection signal) V_(OUT) _(_) _(s) is input to a reference (REF)terminal of the shunt regulator 206. The shunt regulator 206 includes anerror amplifier that amplifies the difference between the voltagedetection signal V_(OUT) _(_) _(S) and a reference voltage V_(REF) (notshown) so as to generate an error current I_(ERR) that corresponds tothe difference, which is drawn (as a sink current) via thelight-emitting element (light-emitting diode) on the input side of thephotocoupler 204.

A feedback current I_(FB) flows through a light-receiving element(phototransistor) on the output side of the photocoupler 204 accordingto the error current I_(ERR) that flows on the secondary side. Thefeedback current I_(FB) is smoothed by means of a resistor and acapacitor, and is input to a feedback (FB) terminal of the primary-sidecontroller 202. The primary-side controller 202 adjusts the duty ratioof the switching transistor M1 based on the voltage (feedback voltage)V_(FB) at the FB terminal.

The secondary-side controller 300 r switches on and off the synchronousrectification transistor M2 in synchronization with the switching of theswitching transistor M1. The secondary-side controller 300 r includes asynchronous rectification controller 304 and a driver 306. Thesynchronous rectification controller 304 generates a pulse signal S1 insynchronization with the switching of the switching transistor M1. Forexample, when the switching transistor M1 turns off, the synchronousrectification controller 304 sets the pulse signal S1 to a first state(e.g., high level) configured as an instruction to turn on thesynchronous rectification transistor M2. When the secondary currentI_(S) that flows through the secondary winding W2 becomes substantiallyzero in an on period of the synchronous rectification transistor M2, thesynchronous rectification controller 304 sets the pulse signal S1 to asecond state (low level) configured as an instruction to turn off thesynchronous rectification transistor M2.

The driver 306 switches on and off the synchronous rectificationtransistor M2 according to the pulse signal S1. The above is the overallconfiguration of the AC/DC converter 100 r.

As a result of investigating the secondary-side controller 300 r, thepresent inventors have come to recognize the following problems.

In order to generate the pulse signal S1, in many cases, thesecondary-side controller 300 r performs time measurement. The timemeasurement result may be used for edge blanking, a timing controloperation for tuning on or turning off the synchronous rectificationtransistor M2, or a control operation for controlling the upper limit orthe lower limit of the on time or the off time. Such a time period(which will be referred to as the “control time” hereafter) is requiredto be set as appropriate according to the time constant of the circuitelements of the output circuit 210. Accordingly, in many cases, thesecondary-side controller 300 r is configured to have a terminal (whichwill be referred to as the “SET terminal” hereafter) that allows thecontrol time to be set via an external circuit.

In many cases, the SET terminal is connected to an external resistor oran external capacitor. With a typical example, a timer circuit isconfigured as a combination of a capacitor, a current source thatcharges the capacitor, and a voltage comparator that compares thevoltage across the capacitor with a threshold voltage. With aconfiguration in which the SET terminal is connected to a settingresistor R_(S)ET configured as an external resistor, the current valuegenerated by the current source may be adjusted according to the settingresistor R_(SET). Alternatively, with such a configuration, thethreshold voltage may be adjusted according to the setting resistorR_(SET). Also, as an another configuration, the SET terminal may beconnected to an external capacitor.

With the secondary-side controller 300 r having such a SET terminal, ifa short circuit (short circuit to a power supply or otherwise to theground) or otherwise an open circuit occurs in the SET terminal due todust or a fault in the mounting of the SET terminal, such an arrangementis not capable of measuring the control time with high precision. Thisleads to an abnormal operation of the synchronous rectificationtransistor M2.

SUMMARY OF THE INVENTION

The present invention has been made in order to solve such a problem.Accordingly, it is an exemplary purpose of an embodiment of the presentinvention to provide a secondary-side controller which is capable ofpreventing an abnormal operation thereof.

An embodiment of the present invention relates to a secondary-sidecontroller that is arranged on a secondary side of an insulatedsynchronous rectification DC/DC converter, and that controls asynchronous rectification transistor. The secondary-side controllercomprises: a set terminal that is connected in use to an externalcircuit element; a synchronous rectification controller that generates apulse signal based on a control time determined according to a state ofthe set terminal; a driver that switches on and off the synchronousrectification transistor according to the pulse signal; and an abnormalstate detection circuit that is capable of detecting an open-circuitstate and/or a short-circuit state that can occur in the set terminal,and that asserts a detection signal upon detection of such anopen-circuit state and/or a short-circuit state. When the detectionsignal is asserted, the secondary-side controller instructs aprimary-side controller arranged on a primary side of the DC/DCconverter to suspend a switching operation of a switching transistor.

With such an embodiment, when abnormal measurement of the control timeoccurs due to the set terminal being in an open-circuit state or ashort-circuit state, the primary-side controller is notified of this soas to suspend the switching operation. Such an arrangement is capable ofsuppressing a malfunction, thereby providing improved reliability.

Also, the secondary-side controller may further comprise: a failterminal connected in use to an input side of a fail notificationphotocoupler; and a fail circuit that drives the fail notificationphotocoupler connected to the fail terminal when the detection signal isasserted. Also, the primary-side controller may suspend the switchingoperation of the switching transistor according to a state of an outputside of the fail notification photocoupler.

Also, the secondary-side controller may further comprise: a shuntregulator output terminal connected in use to an input side of afeedback photocoupler; a shunt regulator that generates an error currentthat corresponds to an output voltage of the DC/DC converter, and thatsupplies the error current thus generated to the feedback photocouplerconnected to the shunt regulator output terminal; and a fail circuitthat drives the feedback photocoupler connected to the shunt regulatoroutput terminal when the detection signal is asserted.

In this case, the feedback photocoupler is also used as a failnotification photocoupler, thereby allowing the number of circuitelements to be reduced.

Also, an external resistor may be connected in use to the set terminal.Also, the abnormal state detection circuit may comprise: a firstcapacitor; a charger circuit that charges the first capacitor using afirst current that is inversely proportional to a resistance value ofthe resistor; a discharger circuit that discharges the first capacitorwith a predetermined second current; and an open circuit detectioncomparator that compares a voltage across the first capacitor with athreshold voltage set for detecting an open circuit.

When an open circuit occurs in the set terminal, the first currentbecomes zero. In this state, the first capacitor is discharged with thesecond current, which reduces the voltage across the first capacitor.Thus, such an arrangement is capable of detecting an open-circuit faultbased on the voltage across the first capacitor.

Also, the abnormal state detection circuit may further comprise a shortcircuit detection comparator that compares a voltage at the set terminalwith a threshold voltage set for detecting a short circuit.

When the set terminal is short-circuited to the ground, the voltage atthe set terminal falls to a voltage in the vicinity of 0 V. On the otherhand, when the set terminal is short-circuited to the power supply, thevoltage at the set terminal rises to a voltage in the vicinity of thepower supply voltage. Thus, such an arrangement is capable of detecting,based on the voltage at the set terminal, a short-circuit faultincluding a fault in which the set terminal is short-circuited to theground and a fault in which the set terminal is short-circuited to thepower supply.

Also, when the detection signal remains in an asserted state for apredetermined period of time, the fail circuit may drive a photocouplerto be driven. Such an arrangement is capable of masking an assertion ofthe detection signal when it occurs for only a very short period oftime. Thus, such an arrangement is capable of preventing false detectionof the short-circuit state and the open-circuit state.

Also, the fail circuit may comprise: a second capacitor; a currentsource that charges the second capacitor; a discharger transistor thatis arranged in parallel with the second capacitor, and that is turned onwhen the detection signal is negated; and a voltage comparator thatasserts a fail signal when a voltage across the second capacitor exceedsa threshold voltage. Also, the secondary-side controller may drive thephotocoupler to be driven, in response to assertion of the fail signal.

Also, when the fail signal is consecutively asserted a predeterminednumber of times, the fail circuit may drive the photocoupler to bedriven.

Also, the synchronous rectification controller may comprise: a pulsegenerator that generates a pulse signal based on a voltage across bothterminals of the synchronous rectification transistor, that sets thepulse signal to an on level configured as an instruction to turn on thesynchronous rectification transistor when the turn-off of the switchingtransistor arranged on the primary side of the DC/DC converter isdetected, and that sets the pulse signal to an off level configured asan instruction to turn off the synchronous rectification transistor whenit is detected that a current that flows through a secondary winding ofa transformer becomes substantially zero; a driver that switches on andoff the synchronous rectification transistor according to the pulsesignal; and a forced turn-off circuit that forcibly turns off thesynchronous rectification transistor after a predetermined time-upperiod elapses after the turn-on of the switching transistor isdetected. Also, the control time may be configured as the time-upperiod.

The time-up period may be set to be shorter than the switching period ofthe switching transistor. In a case in which the switching frequency isconfigured as a variable frequency, the time-up period may be set to beshorter than the period that corresponds to the maximum frequency.

In a given cycle, the switching transistor is turned on and turned off,following which the synchronous rectification transistor is turned on.Such an embodiment ensures that, in the next cycle, the synchronousrectification transistor is turned off before the switching transistoris turned on, thereby solving a problem that can occur in the continuousmode.

Also, after the time-up period elapses after the turn-on of theswitching transistor is detected, the forced turn-off circuit may switchthe pulse signal to the off level.

This allows the synchronous rectification transistor to be forciblyturned off

Also, the pulse generator may comprise: a set signal generating unitthat generates a set signal which is asserted when the turn-off of theswitching transistor is detected; a reset signal generating unit thatgenerates a reset signal which is asserted when it is detected that thecurrent that flows through the secondary winding of the transformerbecomes substantially zero; and a flip-flop that generates the pulsesignal which is switched to an on level when the set signal is asserted,and which is switched to an off level when the reset signal is asserted.

Also, the forced turn-off circuit may generate a forced turn-off signalwhich is asserted after the time-up period elapses after the turn-on ofthe switching transistor is detected. Also, when at least one from amongthe reset signal and the forced turn-off signal is asserted, theflip-flop may set the pulse signal to an off level.

Also, when the reset signal is asserted, the forced turn-off circuit maystart time measurement.

In the continuous mode, the secondary current becomes zero as a resultof the turn-on of the switching transistor. Thus, such an embodiment iscapable of detecting, based on the assertion of the reset signal,whether or not the switching transistor turns on.

The set signal generating unit may comprise a first comparator thatcompares the voltage across both terminals of the synchronousrectification transistor with a first threshold voltage, and thatoutputs a set signal that corresponds to the comparison result. Thereset signal generating unit may comprise a second comparator thatcompares the voltage across both terminals of the synchronousrectification transistor with a second threshold voltage, and thatoutputs a reset signal that corresponds to the comparison result.

Also, the secondary-side controller according to an embodiment mayfurther comprise a third comparator that compares a voltage across bothterminals of the synchronous rectification transistor with a thirdthreshold voltage configured as a predetermined positive voltage. Also,when the voltage across both terminals of the synchronous rectificationtransistor crosses the third threshold voltage, the time measurementoperation of the forced turn-off circuit may be reset.

When the synchronous rectification transistor is turned off in thediscontinuous mode, the voltage across both terminals of the synchronousrectification transistor rises, following which resonance oscillationoccurs in this voltage. With such an embodiment, by comparing thevoltage across both terminals of the synchronous rectificationtransistor with the third threshold voltage, such an arrangement iscapable of detecting such a rise in this voltage in the discontinuousmode. In the discontinuous mode, in this case, such an arrangement iscapable of resetting time measurement, thereby overriding the forcedturn-off function.

The third threshold voltage may be the output voltage of the DC/DCconverter or otherwise a voltage that is offset with respect to theoutput voltage.

In the discontinuous mode, when the synchronous rectification transistorturns off, the voltage across both terminals of the synchronousrectification transistor rises, following which this voltage settles tothe voltage level of the output voltage. Thus, by setting the thirdthreshold voltage based on the output voltage, such an arrangement iscapable of detecting the discontinuous mode in a sure manner.

Another embodiment of the present invention also relates to asecondary-side controller. The secondary-side controller comprises: afirst comparator that compares a voltage across both terminals of thesynchronous rectification transistor with a first threshold voltage, andthat asserts a set signal when the voltage across both terminals of thesynchronous rectification transistor becomes lower than the firstthreshold voltage; a second comparator that compares the voltage acrossboth terminals of the synchronous rectification transistor with a secondthreshold voltage, and that asserts a reset signal when the voltageacross both terminals of the synchronous rectification transistorbecomes higher than the second threshold voltage; a flip-flop thatgenerates a pulse signal which is switched to an on level when the setsignal is asserted, and which is switched to an off level when the resetsignal is asserted; a forced turn-off circuit that forcibly turns offthe synchronous rectification transistor after a predetermined time-upperiod elapses after the reset signal is asserted; a set terminal thatis connected in use to an external circuit element so as to determinethe time-up period based on a circuit constant of the circuit element;and an abnormal state detection circuit that is capable of detecting anopen-circuit state and/or a short-circuit state that can occur in theset terminal, and that asserts a detection signal upon detection of suchan open-circuit state and/or short-circuit state. When the detectionsignal is asserted, the secondary-side controller instructs aprimary-side controller arranged on a primary side of the DC/DCconverter to suspend a switching operation of a switching transistor.

Also, the forced turn-off circuit may generate a forced turn-off signalwhich is asserted after the time-up period elapses after the resetsignal is asserted. Also, when at least one from among the reset signaland the forced turn-off signal is asserted, the flip-flop may switch thepulse signal to an off level.

The secondary-side controller may further comprise a third comparatorthat compares the voltage across both terminals of the synchronousrectification transistor with a third threshold voltage having apredetermined positive voltage value. When the voltage across bothterminals of the synchronous rectification transistor crosses the thirdthreshold voltage, the time measurement operation of the forced turn-offcircuit may be reset.

Also, the secondary-side controller may monolithically be integrated ona single semiconductor substrate.

Examples of such a “monolithically integrated” arrangement include: anarrangement in which all the circuit components are formed on asemiconductor substrate; and an arrangement in which principal circuitcomponents are monolithically integrated. Also, a part of the circuitcomponents such as resistors and capacitors may be arranged in the formof components external to such a semiconductor substrate in order toadjust the circuit constants.

By monolithically integrating the circuit on a single chip, such anarrangement allows the circuit area to be reduced, and allows thecircuit elements to have uniform characteristics.

Yet another embodiment of the present invention relates to an insulatedsynchronous rectification DC/DC converter. The DC/DC convertercomprises: a transformer comprising a primary winding and a secondarywinding; a switching transistor connected to the primary winding of thetransformer; a synchronous rectification transistor connected to thesecondary winding of the transformer; a feedback photocoupler; a shuntregulator that is connected to an input side of the feedbackphotocoupler, and that generates an error current that corresponds to anoutput voltage of the DC/DC converter; a primary-side controller that isconnected to an output side of the feedback photocoupler, and thatswitches on and off the switching transistor according to a feedbacksignal received from the feedback photocoupler; and any one of theaforementioned secondary-side controllers that control the synchronousrectification transistor.

The DC/DC converter may be configured as a flyback converter or aforward converter.

Yet another embodiment of the present invention relates to a powersupply apparatus (AC/DC converter). The power supply apparatuscomprises: a filter that filters a commercial AC voltage; a dioderectifier circuit that full-wave rectifies an output voltage of thefilter; a smoothing capacitor that smoothes an output voltage of thediode rectifier circuit so as to generate a DC input voltage; and theaforementioned DC/DC converter that steps down the DC input voltage, andthat supplies the DC input voltage thus stepped down to a load.

Yet another embodiment of the present invention relates to an electronicdevice. The electronic device comprises: a load; a filter that filters acommercial AC voltage; a diode rectifier circuit that full-waverectifies an output voltage of the filter; a smoothing capacitor thatsmoothes an output voltage of the diode rectifier circuit so as togenerate a DC input voltage; and the aforementioned DC/DC converter thatsteps down the DC input voltage, and that supplies the DC input voltagethus stepped down to the load.

Yet another embodiment of the present invention relates to an ACadapter. The AC adapter comprises: a filter that filters a commercial ACvoltage; a diode rectifier circuit that full-wave rectifies an outputvoltage of the filter; a smoothing capacitor that smoothes an outputvoltage of the diode rectifier circuit so as to generate a DC inputvoltage; and the aforementioned DC/DC converter that steps down the DCinput voltage so as to generate a DC output voltage.

It is to be noted that any arbitrary combination or rearrangement of theabove-described structural components and so forth is effective as andencompassed by the present embodiments. Moreover, this summary of theinvention does not necessarily describe all necessary features so thatthe invention may also be a sub-combination of these described features.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will now be described, by way of example only, withreference to the accompanying drawings which are meant to be exemplary,not limiting, and wherein like elements are numbered alike in severalFigures, in which:

FIG. 1 is a block diagram showing a basic configuration of an AC/DCconverter investigated by the present inventors;

FIG. 2 is a circuit diagram showing a DC/DC converter including asecondary-side controller according to a first embodiment;

FIG. 3 is a circuit diagram showing a DC/DC converter according to afirst modification;

FIG. 4 is a circuit diagram showing a DC/DC converter according to asecond modification;

FIG. 5 is a circuit diagram showing a DC/DC converter including asecondary-side controller according to a second embodiment;

FIG. 6 is a circuit diagram showing a DC/DC converter including asecondary-side controller according to a third embodiment;

FIG. 7 is a circuit diagram showing an example configuration of anabnormal state detection circuit;

FIG. 8 is a circuit diagram showing an example configuration of a failcircuit;

FIG. 9 is a circuit diagram showing an example configuration of asecondary-side controller;

FIG. 10 is an operation waveform diagram showing the operation of aDC/DC converter including no forced turn-off circuit in the continuousmode;

FIG. 11 is an operation waveform diagram showing the operation of theDC/DC converter shown in FIG. 9 in the continuous mode;

FIG. 12 is an operation waveform diagram showing the operation of theDC/DC converter shown in FIG. 9 in the discontinuous mode;

FIG. 13 is a circuit diagram showing a secondary-side controlleraccording to a first example configuration;

FIG. 14 is a circuit diagram showing a secondary-side controlleraccording to a second example configuration;

FIG. 15 is a diagram for describing the problems that can occur in thesecondary-side controller shown in FIG. 13;

FIG. 16 is an operation waveform diagram showing the operation of thesecondary-side controller shown in FIG. 14 in the discontinuous mode;

FIG. 17A is a circuit diagram showing an example configuration of aforced turn-off circuit, and FIG. 17B is a circuit diagram showing acurrent source shown in FIG. 17A;

FIG. 18 is a diagram showing an AC adapter including an AC/DC converter;

FIGS. 19A and 19B are diagrams each showing an electronic deviceincluding an AC/DC converter;

FIG. 20 is a circuit diagram showing a DC/DC converter; and

FIG. 21 is a circuit diagram showing a secondary-side controlleraccording to a second modification.

DETAILED DESCRIPTION OF THE INVENTION

The invention will now be described based on preferred embodiments whichdo not intend to limit the scope of the present invention but exemplifythe invention. All of the features and the combinations thereofdescribed in the embodiment are not necessarily essential to theinvention.

In the present specification, the state represented by the phrase “themember A is connected to the member B” includes a state in which themember A is indirectly connected to the member B via another member thatdoes not affect the electric connection therebetween, in addition to astate in which the member A is physically and directly connected to themember B.

Similarly, the state represented by the phrase “the member C is providedbetween the member A and the member B” includes a state in which themember A is indirectly connected to the member C, or the member B isindirectly connected to the member C via another member that does notaffect the electric connection therebetween, in addition to a state inwhich the member A is directly connected to the member C, or the memberB is directly connected to the member C.

FIRST EMBODIMENT

FIG. 2 is a circuit diagram showing a DC/DC converter 200 including asecondary-side controller 300 according to a first embodiment. The DC/DCconverter 200 is applicable to the AC/DC converter in the same way aswith the DC/DC converter 200 r shown in FIG. 1. Also, the DC/DCconverter 200 has the same basic configuration as that of the DC/DCconverter 200 r shown in FIG. 1.

The secondary-side controller 300 includes a power supply (VCC)terminal, a switching output (OUT) terminal, a drain (V_(D)) terminal,and a ground (GND) terminal. The secondary-side controller 300 isconfigured as a function IC (Integrated Circuit) integrally formed on asingle semiconductor substrate. The secondary-side controller 300 ishoused in a single package together with the synchronous rectificationtransistor M2. That is to say, the secondary-side controller 300 and thesynchronous rectification transistor M2 are monolithically integrated asa single module.

A DC voltage (here, the output voltage V_(OUT)) generated on thesecondary side of the DC/DC converter 200 is supplied to the VCCterminal of the secondary-side controller 300. The secondary-sidecontroller 300 operates using the voltage thus received via the VCCterminal as a main power supply. The V_(D) terminal is connected to thedrain of the synchronous rectification transistor M2. The OUT terminalis connected to the gate of the synchronous rectification transistor M2.The GND terminal is connected to an electric potential to be used as areference voltage for the secondary-side controller 300. With thepresent embodiment, the reference electric potential on the secondaryside, i.e., the ground voltage V_(GND), is supplied to the GND terminal.

Furthermore, the secondary-side controller 300 includes a set (SET)terminal. In use, the SET terminal is connected to an external circuitelement. In the present embodiment, this circuit element is configuredas a resistor R_(SET). The length of at least one time period (controltime), which is to be used to drive the synchronous rectificationtransistor M2, is set according to the resistance value of the resistorR_(SET).

The secondary-side controller 300 includes a synchronous rectificationcontroller 304, a driver 306, an abnormal state detection circuit 320,and a fail circuit 322.

The synchronous rectification controller 304 generates a pulse signal S1based on the state of the SET terminal, i.e., based on the control timedetermined according to the resistance value of the resistor R_(SET).The control time may be used for (1) edge blanking, (2) a timing controloperation for tuning on or turning off the synchronous rectificationtransistor M2, (3) a control operation for controlling the upper limitor the lower limit of the on time or the off time, or the like. With thepresent invention, the usage of the control time is not restricted inparticular.

For example, the synchronous rectification controller 304 generates thepulse signal S1 based on the drain voltage V_(D) _(_) _(S) of thesynchronous rectification transistor M2. The secondary-side controller300 is arranged such that its GND terminal is connected to the commonground line together with the source of the synchronous rectificationtransistor M2. The secondary-side controller 300 operates with thesource voltage V_(GND) as its reference voltage. Thus, the drain voltageV_(D) _(_) _(S) at the V_(D) terminal is the same as the voltage(drain-source voltage V_(DS)) across both terminals of the synchronousrectification transistor M2.

The configuration and the operation of the synchronous rectificationcontroller 304 are not restricted in particular. Rather, the synchronousrectification controller 304 may be configured using known orprospectively available techniques. For example, when the synchronousrectification controller 304 detects that the switching transistor M1arranged on the primary side of the DC/DC converter 200 turns off, thesynchronous rectification controller 304 may set the pulse signal S1 toan on level (e.g., high level) configured as an instruction to turn onthe synchronous rectification transistor M2. Furthermore, when thesynchronous rectification controller 304 detects that the current I_(S)that flows through the secondary winding W2 of the transformer T1becomes substantially zero, the synchronous rectification controller 304may set the pulse signal S1 to an off level (e.g., low level) configuredas an instruction to turn off the synchronous rectification transistorM2. The driver 306 switches on and off the synchronous rectificationtransistor M2 according to the pulse signal S1.

During the on period of the switching transistor M1, the voltage acrossboth ends of the secondary winding W2 is represented by(−V_(IN)×N_(S)/N_(P)). Accordingly, the drain voltage V_(D) _(_) _(S)(i.e., drain-source voltage VDs) of the synchronous rectificationtransistor M2 is represented by (V_(D) _(_)_(S)=V_(OUT)+V_(IN)×N_(S)/N_(P)). Here, N_(P) and N_(S) represent thenumber of turns of the primary winding W1 and the number of turns of thesecondary winding W2, respectively.

When the switching transistor M1 turns off, the secondary current I_(S)flows from the source to the drain of the synchronous rectificationtransistor M2. In this state, the drain-source voltage becomes anegative voltage. In the continuous mode, when the switching transistorM1 turns on, the secondary current I_(S) becomes zero. In this stage,the drain voltage V_(D) jumps up again to a value represented by(V_(D)=V_(OUT)+V_(IN)×N_(S)/N_(P)). In the discontinuous mode, when thesynchronous rectification transistor M2 turns on, the energy stored inthe transformer T1 decreases. In this state, the secondary current I_(S)also decreases, which reduces the absolute value of the drain-sourcevoltage V_(DS). Eventually, the secondary current I_(S) becomessubstantially zero. In this stage, the drain-source voltage V_(DS) alsobecomes substantially zero. In this state, ringing occurs in the drainvoltage V_(D) _(_) _(S).

Using this mechanism, the synchronous rectification controller 304 maygenerate the pulse signal S1 based on the drain voltage (drain-sourcevoltage) of the synchronous rectification transistor M2.

The driver 306 switches on and off the synchronous rectificationtransistor M2 according to the pulse signal S1.

The abnormal state detection circuit 320 is capable of detecting anopen-circuit state and/or a short-circuit state that can occur in theSET terminal. When the abnormal state detection circuit 320 detectseither the open-circuit state or the short-circuit state, the abnormalstate detection circuit 320 asserts (sets to the high level, forexample) a detection signal S11. When the abnormal state detectioncircuit 320 detects neither the open-circuit state nor the short-circuitstate, the abnormal state detection circuit 320 negates (sets to the lowlevel) the detection signal S11.

When the detection signal S11 is asserted, the secondary-side controller300 instructs the primary-side controller 202, which is arranged on theprimary side of the DC/DC converter 200, to suspend the switchingoperation of the switching transistor M1. Furthermore, when thedetection signal S11 is asserted, the synchronous rectificationcontroller 304 turns off the synchronous rectification transistor M2.

Specifically, the secondary-side controller 300 is provided with a fail(FAIL) terminal. In use, the FAIL terminal is connected to the inputside of a fail notification photocoupler 205. When the detection signalS11 is asserted, the fail circuit 322 drives the fail notificationphotocoupler 205 connected to the FAIL terminal.

The primary-side controller 202 suspends the switching operation of theswitching transistor M1 according to the state of the output side of thefail notification photocoupler 205. When the fail circuit 322 drives thefail notification photocoupler 205, a fail current I_(FAIL) _(_) _(IN)flows on the input side of the fail notification photocoupler 205, and afail current I_(FAIL) _(_) _(OUT) flows on the output side thereof. Theprimary-side controller 202 is capable of detecting, based on the failcurrent I_(FAIL) _(_) _(OUT)an abnormal state that can occur in the SETterminal included in the secondary-side controller 300.

In the DC/DC converter 200 shown in FIG. 2, the output side of the failnotification photocoupler 205 is connected to an FB terminal of theprimary-side controller 202 together with the output side of thefeedback photocoupler 204.

The above is the configuration of the secondary-side controller 300 andthe configuration of the DC/DC converter 200 using the secondary-sidecontroller 300 according to the embodiment. Next, description will bemade regarding the operation thereof.

[Normal Operation]

When the resistor R_(SET) is connected normally to the SET terminal, thedetection signal S11 is negated. In this state, the fail circuit 322does not drive the fail notification photocoupler 205. Accordingly, thelight-emitting element of the fail notification photocoupler 205 emitsno light. In this state, the fail current I_(FAIL) _(_) _(OUT) does notflow. In this case, the feedback voltage V_(FB) applied to the FBterminal of the primary-side controller 202 is adjusted by means of theshunt regulator 206 and the feedback photocoupler 204 such that thevoltage detection signal V_(OUT) _(_) _(S) approaches the target valueV_(REF).

[Abnormal Operation]

When an open circuit or otherwise a short circuit occurs in the SETterminal, the detection signal S11 is asserted. In response to this, thefail circuit 322 drives the fail notification photocoupler 205. In thisstate, the light-emitting element of the fail notification photocoupler205 emits light, and the fail current I_(FAIL) _(_) _(OUT) flows. As aresult of the flow of the fail current I_(FAIL) _(_) _(OUT), a capacitorconnected to the FB terminal is discharged. Accordingly, the feedbackvoltage V_(FB) drops to a value in the vicinity of the ground voltage (0V). In this state, the duty ratio of the switching transistor M1 becomeszero, which results in suspension of the switching operation of theswitching transistor M1. Furthermore, in response to the assertion ofthe detection signal S11, the driver 306 turns off the synchronousrectification transistor M2, thereby suspending the switching operationthereof.

The above is the operation of the secondary-side controller 300. When anopen circuit or otherwise a short circuit occurs in the SET terminal,the control time to be used as a reference period for the synchronousrectification controller 304 becomes excessively long or otherwisebecomes excessively short. Accordingly, in this case, in some cases, thesynchronous rectification transistor M2 does not turn on in a period inwhich it is to be turned on, or in some cases, the synchronousrectification transistor M2 turns on in a period in which it is to beturned off For example, in the on period of the switching transistor M1,the synchronous rectification transistor M2 is to be required to beturned off If the synchronous rectification transistor M2 turns onabnormally in this period, an overvoltage is applied across bothterminals of the synchronous rectification transistor M2. In some cases,this leads to adverse effects on the reliability of the synchronousrectification transistor M2. Otherwise, if the current that flowsthrough the secondary winding W2 suddenly changes due to abnormalturn-on or otherwise turn-off of the synchronous rectificationtransistor M2, an overvoltage occurs at the primary winding W1. In somecases, this leads to adverse effects on the reliability of the switchingtransistor M1.

The secondary-side controller 300 according to the embodiment detects anopen circuit and/or a short circuit that can occur in the SET terminal(i.e., at least one from among an open circuit and a short circuit).Furthermore, upon detection of an abnormal state, the secondary-sidecontroller 300 suspends the operation of the DC/DC converter 200. Thus,such an arrangement is capable of preventing an abnormal operation,thereby providing improved reliability.

Next, description will be made regarding a modification of the DC/DCconverter 200 employing the secondary-side controller 300.

FIG. 3 is a circuit diagram showing a DC/DC converter 200 a according toa first modification. In this modification, the primary-side controller202 includes a fail (FAIL) terminal for receiving a signal thatindicates a fail notice from the secondary-side controller 300. Theoutput side of the fail notification photocoupler 205 is connected tothe FAIL terminal. The primary-side controller 202 detects the presenceor absence of the fail current I_(FAIL) _(_) _(OUT). Upon detection ofthe flow of the fail current I_(FAIL) _(_) _(OUT), the primary-sidecontroller 202 suspends the switching operation of the switchingtransistor M1.

FIG. 4 is a circuit diagram showing a DC/DC converter 200 b according toa second modification. In this modification, the FAIL terminal of thesecondary-side controller 300 is connected to the input side of thefeedback photocoupler 204. When the detection signal S11 is asserted soas to provide a flow of the fail current I_(FAIL) _(_) _(IN) that islarger than the error current I_(ERR), this increases the current I_(FB)that flows on the output side of the feedback photocoupler 204. In thiscase, the capacitor connected to the FB terminal is discharged. Thisreduces the feedback voltage V_(FB) to a value in the vicinity of theground voltage (0 V). In this state, the duty ratio of the switchingtransistor M1 becomes zero, which suspends the switching operation ofthe switching transistor M1.

That is to say, in the second modification, the feedback photocoupler204 also provides the same effect as that provided by the failnotification photocoupler 205. Furthermore, the output current I_(FB) ofthe feedback photocoupler 204 also provides the same effect as thatprovided by the fail current I_(FAIL) _(_) _(OUT).

SECOND EMBODIMENT

FIG. 5 is a DC/DC converter 200 c including a secondary-side controller300 c according to a second embodiment. The secondary-side controller300 c has the same configuration as that of the secondary-sidecontroller 300 shown in FIG. 2 except that a shunt regulator 206 isbuilt into the secondary-side controller 300 c. The shunt regulator 206includes a transistor M3 and an error amplifier 207. The voltagedetection signal V_(OUT) _(_) _(S) is input to the input terminal(SH_IN) of the shunt regulator 206. The error amplifier 207 amplifiesthe difference between the voltage detection signal V_(OUT) _(_) _(S)and the reference voltage V_(REF). The transistor M3 is connected to theoutput terminal (SH_OUT) of the shunt regulator 206. The output V_(ERR)of the error amplifier 207 is input to the gate of the transistor M3. Ina case in which the transistor M3 is configured as a P-channel MOSFET orotherwise a PNP bipolar transistor, the error amplifier 207 maypreferably be arranged such that its inverting input terminal and itsnon-inverting input terminal are mutually exchanged.

With the secondary-side controller 300 c, such an arrangement alsoprovides the same effects as those provided by the first embodiment.Also, the secondary-side controller 300 c may be applied to the DC/DCconverter 200 a shown in FIG. 3 and the DC/DC converter 200 b shown inFIG. 4.

THIRD EMBODIMENT

FIG. 6 is a circuit diagram showing a DC/DC converter 200 d including asecondary-side controller 300 d according to a third embodiment. A shuntregulator 206 is built into the secondary-side controller 300 d, as witha configuration shown in FIG. 5. When the detection signal S11 isasserted, a fail circuit 322 d drives the feedback photocoupler 204connected to the SH_OUT terminal.

For the secondary-side controller 300 d, it can be understood that theSH_OUT terminal also provides the same effect as that provided by theFAIL terminal, and that the feedback photocoupler 204 provides the sameeffect as that provided by the fail notification photocoupler 205.

Next, description will be made regarding a specific exampleconfiguration of the secondary-side controller 300. It should be notedthat the present invention encompasses various arrangements derivedbased on the first through third embodiments. That is to say, thepresent invention is not restricted to such a specific configurationdescribed below.

FIG. 7 is a circuit diagram showing an example configuration of theabnormal state detection circuit 320.

In use, the SET terminal is connected to the resistor R_(SET) configuredas an external component. The abnormal state detection circuit 320includes a first capacitor C11, a charger circuit 360, a dischargercircuit 362, and an open circuit detection comparator 364. The chargercircuit 360 charges the first capacitor C11 using a first current I1that is inversely proportional to the resistance value of the resistorR_(SET).

The charger circuit 360 may include a constant current circuit (V/Iconverter circuit) 368 and a current mirror circuit 370. The constantcurrent circuit 368 includes an error amplifier 372 and a transistor374. The constant current circuit 368 applies a reference voltageV_(REF) to the SET terminal. A current I_(SET), which is represented byI_(SET)=V_(REF)/R_(SET), flows through the transistor 374 and theresistor R_(SET). The current mirror circuit 370 mirrors the currentI_(SET) so as to output the first current I1.

The discharger circuit 362 discharges the first capacitor C11 with apredetermined second current I2. The open circuit detection comparator364 compares the voltage V_(C11) across the first capacitor C11 with athreshold voltage V_(OPEN) set for detecting an open circuit. The outputof the open circuit detection comparator 364 is used as a detectionsignal OPEN_DET which indicates an open-circuit fault.

Furthermore, the abnormal state detection circuit 320 includes a shortcircuit detection comparator 366. The charger circuit 360 compares thevoltage V_(SET) at the SET terminal with a threshold voltage V_(SHORT)for detecting a short circuit. The output of the short circuit detectioncomparator 366 is used as a detection signal SHORT_DET which indicates ashort-circuit fault.

Next, description will be made regarding the operation of the abnormalstate detection circuit 320.

[Open Circuit Detection]

When an open circuit occurs in the SET terminal, the current I_(SET) andthe first current I1 become zero. Accordingly, the first capacitor C11is discharged with the second current I2. This reduces the voltageV_(C11) across the first capacitor C11. When the voltage V_(C11) becomeslower than a threshold voltage V_(OPEN), the output OPEN_DET of the opencircuit detection comparator 364 is asserted (set to the high level).

[Short Circuit Detection]

In the normal operation, the voltage V_(SET) at the SET terminal isequal to the reference voltage V_(REF). However, when the SET terminalis short-circuited to the ground, the voltage V_(SET) at the SETterminal drops to a value in the vicinity of 0 V. Accordingly, bysetting the threshold voltage V_(SHORT) to a value (e.g., 0.2 V) in thevicinity of the ground voltage, such an arrangement is capable ofdetecting a state in which the SET terminal is short-circuited to theground. On the other hand, when the SET terminal is short-circuited tothe power supply, the voltage V_(SET) at the SET terminal rises up to avalue in the vicinity of the power supply voltage. Thus, by setting thethreshold voltage V_(SHORT) to a value in the vicinity of the powersupply voltage, such an arrangement is capable of detecting a state inwhich the SET terminal is short-circuited to the power supply. It shouldbe noted that the configuration of the abnormal state detection circuit320 is not restricted to such an arrangement shown in FIG. 7. Also, theabnormal state detection circuit 320 may be configured using knowntechniques.

FIG. 8 is a circuit diagram showing an example configuration of the failcircuit 322. When the assertion of the detection signal S11 (i.e.,OPEN_DET or otherwise SHORT_DET) continues for a predetermined timeperiod, the fail circuit 322 drives a photocoupler to be driven(feedback photocoupler 204 or otherwise the fail notificationphotocoupler 205). Such an arrangement is capable of masking anassertion of the detection signal S11 when it occurs for only a veryshort period of time. Thus, such an arrangement is capable of preventingfalse detection of the short-circuit state and the open-circuit state.

The fail circuit 322 mainly includes a second capacitor C12, a currentsource 380, a discharger transistor 382, and a comparator 384. Thecurrent source 380 charges the second capacitor C12. The dischargertransistor 382 is arranged in parallel with the second capacitor C12.When the detection signal S11 is negated (set to the low level), thedischarger transistor 382 is turned on. When the voltage V_(C12) acrossthe second capacitor C12 exceeds the threshold voltage V_(TIME), thecomparator 384 asserts the fail signal S12.

The fail circuit 322 drives the photocoupler 205 (204) to be driven inresponse to the assertion of the fail signal S12. Specifically, the failcircuit 322 may be connected to the FAIL terminal (SH_OUT terminal).Also, the fail circuit 322 may include a driving transistor 386 thatturns on in response to the assertion of the fail signal S12. Aflip-flop 388 latches the assertion of the fail signal 512. In thisstate, the flip-flop 388 fixes the driving transistor 386 to the onstate.

When the fail signal S12 is consecutively asserted a predeterminednumber of times, the fail circuit 322 may drive the photocoupler 205(204). In order to provide such an operation, the fail circuit 322further includes a discharger transistor 390, a one-shot circuit 392,and a counter 394.

The discharger transistor 390 is arranged in parallel with the secondcapacitor C12. The one-shot circuit 392 generates a signal S13 which isset to the high level for a predetermined time period from the timepoint at which an edge occurs in the fail signal S12. During a period inwhich the signal S13 is set to the high level, the discharger transistor390 is turned on, which resets the voltage across the capacitor C12. Thecounter 394 counts the number of times the output S13 of the one-shotcircuit 392 becomes the high level. When the count value reaches thepredetermined number, the counter 394 latches the driving transistor 386in the on state. When the detection signal S11 is negated, the countvalue of the counter 394 is reset. The above is an example configurationof the fail circuit 322. It should be noted that the configuration ofthe fail circuit 322 is not restricted to such an arrangement shown inFIG. 8.

Next, description will be made regarding an example configuration of thesynchronous rectification controller 304. FIG. 9 is a circuit diagramshowing an example configuration of a secondary-side controller 300 e. Asynchronous rectification controller 304 e has the same configuration asthat shown in FIG. 2 except that the synchronous rectificationcontroller 304 e includes a pulse generator 328 and a forced turn-offcircuit 330. The synchronous rectification controller 304 e isapplicable to the secondary-side controller 300 c shown in FIG. 5 andthe secondary-side controller 300 d shown in FIG. 6.

The pulse generator 328 generates the pulse signal S1 based on thevoltage VDS across both terminals of the synchronous rectificationtransistor M2. Upon detection of the turn-off of the switchingtransistor M1, the pulse generator 328 sets the pulse signal S1 to theon level which instructs the synchronous rectification transistor M2 toturn on. Upon detecting that the current I_(S) that flows through thesecondary winding W2 has become substantially zero, the pulse generator328 sets the pulse signal S1 to the off level which instructs thesynchronous rectification transistor M2 to turn off.

When the synchronous rectification transistor M2 turns on after apredetermined time-up period T_(UP) elapses after detection of theturn-on of the switching transistor M1 (which will be referred to as“forced turn-off timing”), the forced turn-off circuit 330 forciblyturns off the synchronous rectification transistor M2. In the presentembodiment, the forced turn-off circuit 330 asserts a forced turn-offsignal S2 at the forced turn-off timing. With such an arrangement, thepulse signal S1 is switched to the off level (low level) using theforced turn-off signal S2.

The time-up period T_(UP) is set to be shorter than the switching periodT_(SW) set for the switching transistor M1. In a case in which theswitching frequency f_(SW) is changed according to the load, the time-upperiod T_(UP) may preferably be set to be shorter than the periodrepresented by T_(SWMAX) (=1f_(MAX)) that corresponds to the maximumfrequency f_(MAX).

It should be noted that the method for forcibly turning off thesynchronous rectification transistor M2 is not restricted in particular.As another embodiment, for example, a logic gate may be arranged as anadditional component between the synchronous rectification controller304 e and the driver 306 so as to mask the pulse signal S1. Also, alow-side transistor (not shown) of a push-pull output stage of thedriver 306 may be forcibly turned on.

The aforementioned control time corresponds to the time-up periodT_(UP). The SET terminal is used to set the length of the time-up periodT_(UP).

The above is the configuration of the secondary-side controller 300 eshown in FIG. 9. Before description of the operation of thesecondary-side controller 300 shown in FIG. 9, description will be maderegarding problems that can occur in a case in which such a forcedturn-off circuit 330 is not provided.

The present inventors have come to recognize the following problems thatoccur in the DC/DC converter 200 r including no forced turn-off circuit330 as shown in FIG. 1 when it operates in the continuous mode.

FIG. 10 is an operation waveform diagram showing the operation of theDC/DC converter 200 r including no forced turn-off circuit 330 when itoperates in the continuous mode. Before the time point t1, the switchingtransistor M1 turns on. In this state, the drain voltage V_(D) of thesynchronous rectification transistor M2 is represented by(V_(OUT)+V_(IN)×N_(S)/N_(P)). When the transistor M1 is turned off atthe time point t1, the secondary current I_(S) starts to flow throughthe secondary winding W2. In this state, the drain voltage V_(D) becomesa negative voltage. When the synchronous rectification controller 304detects that the drain voltage V_(D) crosses a first threshold voltageV_(TH1) when it drops from the upper side to the lower side, thesynchronous rectification controller 304 sets the pulse signal S1 to afirst state. As a result, the synchronous rectification transistor M2 isturned on.

In the on period of the synchronous rectification transistor M2, theabsolute value of the drain voltage V_(D) decreases according to areduction in the secondary current I_(S). When the switching transistorM1 turns on at a time point t2, the secondary current I_(S) becomeszero. In this state, the drain voltage V_(D) jumps up again to a valuerepresented by (V_(OUT)+V_(IN)×N_(S)/N_(P)). When the drain voltageV_(D) crosses a second threshold voltage V_(TH2) when it rises from thelower side to the upper side, the synchronous rectification controller304 sets the pulse signal S1 to a second state. As a result, thesynchronous rectification transistor M2 is turned off.

With such an arrangement, there is a delay time period τ_(D) from thetime point t2 at which the drain voltage V_(D) crosses the thresholdvoltage V_(TH2) up to a time point t3 at which the synchronousrectification transistor M2 turns off according to a transition of thepulse signal S1 to the second state. During the delay time τ_(D), thesynchronous rectification transistor M2 turns on. In this state, a largevoltage V_(D) occurs across both terminals of the synchronousrectification transistor M2 in a state in which it has an extremely lowimpedance. Accordingly, in some cases, this leads to a problem of alarge amount of current flowing through the synchronous rectificationtransistor M2 (as indicated by the broken line I_(S)′).

During the delay time τ_(D), the large current I_(S)′ flows through thesynchronous rectification transistor M2 via the secondary winding W2.When the synchronous rectification transistor M2 turns off at the timepoint t3, the current I_(S)′ that flows through the secondary winding W2is cut off This generates a high voltage across both ends of thesecondary winding W2 as represented by Vx=dI_(S)′/dt. The high voltageVx induces the voltage Vy across both ends of the primary winding W1 asrepresented by Vy=-Vx×N_(P)/N_(S). In a case in which the voltage Vythus induced is applied to the switching transistor M1, in some cases,this leads to degradation of the reliability of the switching transistorM1.

In order to solve such problems, an approach is conceivable in which theprimary-side controller 202 supplies, to the secondary-side controller300, a timing signal which indicates the turn-on of the switchingtransistor M1. With such an arrangement, the secondary-side controller300 turns off the synchronous rectification transistor M2 before theturn-on of the switching transistor M1.

However, with such an insulated converter, there is a need to provideelectrical insulation between the primary side and the secondary side.Such an arrangement requires an additional photocoupler or a capacitor,leading to a problem of an increased circuit cost.

The above are problems that can occur in the continuous mode. Next,description will be made regarding an operation of the secondary-sidecontroller 300 shown in FIG. 9 for solving such problems.

FIG. 11 is an operation waveform diagram showing the operation of theDC/DC converter 200 shown in FIG. 9 when it operates in the continuousmode. At the time point t1, the switching transistor M1 is turned on.When the switching transistor M1 turns on, the forced turn-off circuit330 starts time measurement. When the time-up period T_(UP) elapses, theforced turn-off signal S2 is asserted. With such an arrangement, thetime-up period T_(UP) is determined so as to satisfy the relationT_(UP)<T_(SW). Thus, the pulse signal S1 is switched to the off levelbefore the time point t4 at which the switching transistor M1 turns onin the next cycle. That is to say, such an arrangement is capable ofturning off the synchronous rectification transistor M2 before the timepoint t4 at which the switching transistor M1 turns on in the nextcycle.

FIG. 12 is an operation waveform diagram showing the operation of theDC/DC converter 200 shown in FIG. 9 when it operates in thediscontinuous mode. In the discontinuous mode, the secondary currentI_(S) becomes substantially zero before the assertion of the forcedturn-off signal S2. Accordingly, the synchronous rectificationtransistor M2 switches on and off without involving forced turning-offaccording to the forced turn-off signal S2.

The above is the operation of the DC/DC converter 200.

With the DC/DC converter 200, as shown in FIG. 11, in the continuousmode, the synchronous rectification transistor M2 turns off before theswitching transistor M1 turns on. Thus, such an arrangement is capableof solving a problem that can occur in the continuous mode. Such anarrangement configured to provide such a control operation does notrequire the primary-side controller 202 to supply, to the secondary-sidecontroller 300, a timing signal that indicates the turn-on of theswitching transistor M1. Thus, such an arrangement requires noadditional component such as a photocoupler or a capacitor used totransmit a timing signal, thereby providing an advantage from the costviewpoint.

With the secondary-side controller 300 e, if an open circuit occurs inthe SET terminal, the time-up period T_(UP) becomes excessively long,leading to a problem in that the configuration of the secondary-sidecontroller 300 e becomes equivalent to that of having no forced turn-offcircuit 330. Thus, in this case, such an arrangement involves theaforementioned problems that can occur in the continuous mode.Conversely, if the SET terminal is short-circuited to the ground, thetime-up period becomes excessively short. This leads to a reduced ontime of the synchronous rectification transistor M2, which becomes acause of abnormal generation of heat.

With the secondary-side controller 300 e shown in FIG. 9, by detectingan open-circuit fault and a short-circuit fault that can occur in theSET terminal, such an arrangement provides improved reliability.

FIG. 13 is a circuit diagram showing a secondary-side controller 300 eaccording to a first example configuration.

The pulse generator 328 includes a set signal generating unit 308, areset signal generating unit 310, and a D flip-flop FF1. Thesecondary-side controller 300 e is arranged such that its GND terminalis connected to the source of the synchronous rectification transistorM2. Accordingly, with the secondary-side controller 300 e, the voltageV_(D) at the VD terminal corresponds to the drain-source voltage of thesynchronous rectification transistor M2.

As described above, (i) when the switching transistor M1 turns off, thepulse generator 328 sets the pulse signal S1 to a first state (highlevel). (ii) When the current I_(S) that flows through the secondarywinding W2 becomes substantially zero in the on period of thesynchronous rectification transistor M2, the pulse generator 328 setsthe pulse signal S1 to a second state (low level).

The set signal generating unit 308 includes a first comparator CMP1 inorder to detect (i) whether or not the switching transistor M1 turnsoff. The first comparator CMP1 compares the drain voltage (drain-sourcevoltage) V_(D) at the VD terminal with a predetermined negative firstthreshold voltage V_(TH1) (e.g., −150 mV). When the drain voltage V_(D)crosses the first threshold voltage V_(TH1), the first comparator CMP1asserts (sets to the high level) a set signal S_(ON). Specifically, whenthe drain voltage V_(D) becomes lower than the threshold voltageV_(TH1), i.e., when the drain-source voltage V_(DS) becomes a negativevoltage, the set signal S_(ON) is set to the high level. The set signalS_(ON) is input to a clock terminal of the D flip-flop FF1. The pulsesignal S1 is switched to the high level in response to a positive edgethat occurs in the set signal S_(ON). Instead of the D flip-flop FF1, anRS flip-flop may be employed.

The reset signal generating unit 310 includes a second comparator CMP2in order to detect (ii) whether or not the secondary current I_(S) thatflows through the secondary winding W2 becomes substantially zero in theon period of the synchronous rectification transistor M2. In the offperiod of the switching transistor M1, the current I_(S) flows from thesource to the drain of the synchronous rectification transistor M2.Thus, the drain-source voltage V_(DS) becomes a negative voltage havingan absolute value that corresponds to the current value of the currentI_(S). Using this mechanism, the second comparator CMP2 compares thedrain voltage V_(D) with a negative threshold voltage V_(TH2) (e.g., −10mV) set to a negative value in the vicinity of zero. When the drainvoltage V_(D) becomes higher than the threshold voltage V_(TH2), thesecond comparator CMP2 asserts (set to the low level) a reset signalS_(OFF). The reset signal S_(OFF) is input to a reset terminal (logicalinversion) of the flip-flop FF1. The pulse signal S1 is switched to thelow level in response to a negative edge of the reset signal S_(OFF).

When at least one from among the reset signal S_(ON) and the forcedturn-off signal S2 is asserted (set to the low level), the flip-flop FF1switches the pulse signal S1 to the off level (low level). In order toprovide such an operation, a logic circuit 332 is provided. The logiccircuit 332 performs a logical operation on the forced turn-off signalS2 and the reset signal S_(OFF), and outputs the logical value thusobtained to a reset terminal (logical inversion) of the flip-flop FF1.With such an arrangement, the logic circuit 332 is configured as an ANDgate. Also, the configuration thereof may be modified as appropriateaccording to the logical values of the corresponding signals.

As shown in FIG. 11, in the continuous mode, the secondary current I_(S)becomes zero according to the turn-on of the switching transistor M1. Inthis stage, the drain voltage V_(D) jumps up. Thus, the timing at whichthe second comparator CMP2 detects that the current becomes zerosubstantially matches the timing at which the switching transistor M1turns on. Using this mechanism, when the reset signal S_(OFF) isasserted, the forced turn-off circuit 330 starts time measurement on theassumption that the switching transistor M1 turns on when the resetsignal S_(OFF) is asserted.

The secondary-side controller 300 e shown in FIG. 13 is capable ofsolving various kinds of problems that can occur in the continuous mode.

FIG. 14 is a circuit diagram showing a secondary-side controller 300 faccording to a second example configuration.

The secondary-side controller 300 f further includes a third comparatorCMP3 in addition to the configuration of the secondary-side controller300 e shown in FIG. 13. The third comparator CMP3 compares thedrain-source voltage V_(DS) of the synchronous rectification transistorwith a predetermined positive third threshold voltage V_(TH3). When theoutput S3 of the third comparator CMP3 indicates that the drain-sourcevoltage V_(DS) crosses the third threshold voltage V_(TH3), the timemeasurement operation of the forced turn-off circuit 330 is reset.

The third threshold voltage V_(TH3) is preferably generated based on theoutput voltage V_(OUT). Specifically, the third threshold voltageV_(TH3) is set to the output voltage V_(OUT) or otherwise a value in thevicinity of the output voltage V_(OUT). Also, the third thresholdvoltage V_(TH3) may be configured as a voltage that is offset withrespect to the output voltage V_(OUT).

The secondary-side controller 300 f shown in FIG. 14 is capable ofsolving a problem that can occur in the secondary-side controller 300 eshown in FIG. 13. First, description will be made regarding the problem.FIG. 15 is a diagram for describing such a problem that can occur in thesecondary-side controller 300 e shown in FIG. 13. In some cases, as theload current I_(OUT) becomes smaller, the primary-side controller 202 ofthe DC/DC converter 200 reduces the switching frequency f_(SW) so as toreduce its switching loss, thereby providing improved efficiency. In acase of employing a combination of such a primary-side controller 202and the secondary-side controller 300 e shown in FIG. 13, such anarrangement is not capable of turning on the synchronous rectificationtransistor M2 when the DC/DC converter 200 operates in the discontinuousmode in a low range of the switching frequency f_(SW), i.e., in a statein which the switching transistor M1 switches on and off with a longswitching period. That is to say, in this state, the synchronousrectification transistor M2 operates in the diode rectification mode.

The secondary-side controller 300 e shown in FIG. 13 uses the outputS_(OFF) of the second comparator CMP2 in order to detect whether or notthe switching transistor M1 turns on. In the continuous mode, as aresult of turning on the switching transistor M1, the secondary currentI_(S) becomes zero. Thus, the time point at which the reset signalS_(OFF) transits indicates that the switching transistor M1 turns on.However, in the discontinuous mode, the secondary current I_(S) becomeszero before the switching transistor M1 turns on. Accordingly, the timepoint at which the reset signal S_(OFF) is asserted does not match thetime point at which the switching transistor M1 turns on.

When the time-up period T_(UP) elapses after the reset signal S_(OFF) isasserted, the synchronous rectification transistor M2 is forcibly turnedoff. The state in which the synchronous rectification transistor M2 isforcibly turned off is canceled according to the next assertion of thereset signal S_(OFF). Accordingly, the set signal S_(ON) is asserted inthe forced turn-off period. Thus, the pulse signal S1 is maintained atthe low level, leading to a problem in that the synchronousrectification transistor M2 cannot be turned on.

That is to say, such a secondary-side controller 300 e has a problem inthat, in some cases, in the discontinuous mode, the synchronousrectification transistor M2 cannot be switched on and off, i.e., itoperates in the diode rectification mode alone.

The secondary-side controller 300 f shown in FIG. 14 is capable ofsolving such a problem. FIG. 16 is an operation waveform diagram showingthe operation of the secondary-side controller 300 f shown in FIG. 14when it operates in the discontinuous mode. When the synchronousrectification transistor M2 turns off in the discontinuous mode, thedrain voltage V_(D) rises. Subsequently, damped oscillation occurs inthe drain voltage V_(D) with the output voltage V_(OUT) as the center ofoscillation. During the damped oscillation, crossing of the thresholdvoltage V_(TH3) by the drain voltage V_(D) repeatedly occurs. The timemeasurement operation of the forced turn-off circuit 330 is reset everytime the drain voltage V_(D) crosses the threshold voltage V_(TH3).Accordingly, in this case, the forced turn-off signal S2 is notasserted. Thus, such an arrangement is capable of maintaining asynchronous rectification operation, i.e., of ensuring the switchingoperation of the synchronous rectification transistor M2, even if itoperates in the discontinuous mode.

FIG. 17A is a circuit diagram showing an example configuration of theforced turn-off circuit 330. The forced turn-off circuit 330 isconfigured as an analog timer circuit including a capacitor C41, acurrent source CS41, a discharger circuit M41, a fourth comparator CMP4,and a one-shot circuit 334. The current source CS41 supplies a currentI_(C) to the capacitor C41. The discharger circuit M41 discharges thecapacitor C41 in response to the reset signal S_(OFF) so as to reset thetime measurement operation. For example, the discharger circuit M41 maybe configured as a transistor. The fourth comparator CMP4 compares avoltage V_(C41) across the capacitor C41 with a predetermined fourththreshold voltage V_(TH4). The one-shot circuit 334 outputs the forcedturn-off signal S2 which is set to a low level (asserted) for apredetermined time period when the voltage V_(C41) across the capacitorC41 exceeds the fourth threshold voltage V_(TH4).

In the secondary-side controller 300 f shown in FIG. 14, the dischargercircuit M41 is configured such that, when at least one from among thereset signal S_(OFF) and the output S3 of the third comparator CMP3 isasserted, the discharger circuit M41 discharges the capacitor C41 so asto reset the time measurement operation. In order to provide such anoperation, an OR gate 336 may be provided.

FIG. 17B is a circuit diagram showing the current source CS41 shown inFIG. 17A. The current source CS41 includes a transistor M42, anoperational amplifier 340, a resistor R_(SET) connected as an externalcomponent to the SET terminal, and a current mirror circuit 342. Acurrent V_(REF)/R_(SET) that corresponds to the external resistorR_(SET) flows through the transistor M42. The current mirror circuit 342mirrors the current V_(REF)/R_(SET), and supplies the mirror currentthus generated to the capacitor C41. Such a configuration allows thetime-up period T_(UP) for the forced turn-off circuit 330 to be setaccording to the resistor R_(SET). The aforementioned abnormal statedetection circuit 320 monitors whether or not an open circuit or a shortcircuit has occurred in the SET terminal.

The forced turn-off circuit 330 may be configured as a digital timeremploying a counter instead of such an analog timer.

[Usage]

Next, description will be made regarding the usage of the DC/DCconverter 200 described in the embodiment.

FIG. 18 is a diagram showing an AC adapter 800 including the AC/DCconverter 100. The AC adapter 800 includes a plug 802, a housing 804,and a connector 806. The plug 802 receives a commercial AC voltageV_(AC) from an unshown electrical outlet. The AC/DC converter 100 ismounted within the housing 804. The DC output voltage V_(OUT) generatedby the AC/DC converter 100 is supplied from the connector 806 to anelectronic device 810. Examples of such an electronic device 810 includelaptop PCs, digital still cameras, digital video cameras, cellularphones, portable audio players, and the like.

FIGS. 19A and 19B are diagrams each showing an electronic device 900including the AC/DC converter 100. The electronic device 900 shown inFIGS. 19A and 19B is configured as a display apparatus. However, theelectronic device 900 is not particularly restricted in kind, as long asit includes a power supply apparatus as an internal component. Examplesof such an electronic device 900 include audio devices, refrigerators,washing machines, vacuum cleaners, etc.

A plug 902 receives commercial AC voltage V_(AC) from an unshownelectrical outlet. The AC/DC converter 100 is mounted within the housing904. The DC output voltage V_(OUT) generated by the AC/DC converter 100is supplied to loads mounted within the same housing 904, examples ofwhich include a microcomputer, DSP (Digital Signal Processor), powersupply circuit, illumination device, analog circuit, digital circuit,etc.

Description has been made above regarding the present invention withreference to the embodiments. The above-described embodiments have beendescribed for exemplary purposes only, and are by no means intended tobe interpreted restrictively. Rather, it can be readily conceived bythose skilled in this art that various modifications may be made bymaking various combinations of the aforementioned components orprocesses, which are also encompassed in the technical scope of thepresent invention. Description will be made below regarding suchmodifications.

[First Modification]

Description has been made in the embodiments regarding an arrangement inwhich the synchronous rectification transistor M2 is arranged on a sidewhere its electric potential is lower than that at the primary windingW1. Also, the synchronous rectification transistor M2 may be arranged ona side that is closer to the output terminal P2. FIG. 20 is a circuitdiagram showing a DC/DC converter 200 g. It should be noted that the SETterminal and the FAIL terminal are not shown.

An auxiliary winding W4 of a transformer T1, a diode D4, and a capacitorC4 form an auxiliary converter that generates a DC voltage V_(CC1) thatis higher than the output voltage V_(OUT). The DC voltage V_(CC1) issupplied to the VCC terminal. The GND terminal of the secondary-sidecontroller 300 is connected to the source of the synchronousrectification transistor M2. The secondary-side controller 300 has thesame configuration as those described in the embodiments. Such amodification provides the same effects as those provided by theembodiment.

[Second Modification]

FIG. 21 is a circuit diagram showing a secondary-side controller 300 haccording to a second modification. The secondary-side controller 300 hincludes a turn-on detection circuit 350 that detects whether or not theswitching transistor M1 turns on. The turn-on detection circuit 350includes a fifth comparator CMP5 that compares the voltage V_(DS) acrossboth terminals of the synchronous rectification transistor M5 with afifth threshold voltage V_(TH5). When the voltage V_(DS) across bothterminals of the synchronous rectification transistor M5 crosses thefifth threshold voltage V_(TH5), the turn-on detection circuit 350asserts a turn-on detection signal S5 which indicates that the switchingtransistor M1 turns on.

The threshold voltage V_(TH5) is preferably set to a voltage in thevicinity of the output voltage V_(OUT) in the same manner as the thirdthreshold voltage V_(TH3). Such an arrangement is capable of detecting arise of the drain voltage V_(D) that occurs accompanying the turn-on ofthe switching transistor M1, thereby detecting whether or not theswitching transistor M1 turns on. It should be noted that, in a case inwhich the fifth threshold voltage V_(TH5) is set to the same level asthat of the second threshold voltage V_(TH2), the secondary-sidecontroller 300 h provides the same operation as that shown in FIG. 13.

[Third Modification]

Description has been made in the embodiment regarding a flybackconverter. Also, the present invention is applicable to a forwardconverter. In this case, multiple synchronous rectification transistorsare arranged on the secondary side of the transformer T1. Thesecondary-side controller may be configured to switch on and off themultiple synchronous rectification transistors. Also, such a convertermay be configured as a quasi-resonant converter.

[Fourth Modification]

Description has been made in the embodiments regarding an arrangement inwhich the resistor R_(SET) is connected to the SET terminal. Also,another kind of circuit element such as a capacitor or the like may beconnected to the SET terminal.

[Fifth Modification]

Description has been made in the embodiments regarding the abnormalstate detection circuit 320 that is capable of detecting both anopen-circuit fault and a short-circuit fault that can occur in the SETterminal. Also, in a case in which there is no need for concern about anopen-circuit fault, the abnormal state detection circuit 320 may detectonly whether or not a short-circuit fault has occurred. Conversely, in acase in which there is no need for concern about a short-circuit fault,the abnormal state detection circuit 320 may detect only whether or notan open-circuit fault has occurred.

[Sixth Modification]

At least one of the switching transistor or the synchronousrectification transistor may be configured as a bipolar transistor or anIGBT.

While the preferred embodiments of the present invention have beendescribed using specific terms, such description is for illustrativepurposes only, and it is to be understood that changes and variationsmay be made without departing from the spirit or scope of the appendedclaims.

1-21. (canceled)
 22. A semiconductor apparatus comprising: a firstterminal; a controller structured to generate a pulse signal accordingto a control time which is determined based on a state of the firstterminal; a first driving circuit structured to output a driving signalaccording to the pulse signal; a detection circuit structured to detectan open-circuit state and/or a short-circuit state that can occur in thefirst terminal, and structured to generate a detection signal inresponse to a detection of the open-circuit state and/or theshort-circuit state; a second terminal which is separate from the firstterminal; and a second driving circuit structured to sink a current viathe second terminal in response to the detection signal.
 23. Thesemiconductor apparatus according to claim 22, wherein the secondterminal is to be coupled to a gate of a synchronous rectificationtransistor.
 24. The semiconductor apparatus according to claim 22,further comprising a third terminal, wherein the controller isstructured to generate the pulse signal according to a state of thethird terminal.
 25. The semiconductor apparatus according to claim 24,wherein the third terminal is to be coupled to a drain of a synchronousrectification transistor.
 26. The semiconductor apparatus according toclaim 22, wherein the second terminal is to be coupled to a photocoupler.
 27. The semiconductor apparatus according to claim 22, whereinthe first terminal is to be coupled to an external resistor.
 28. Thesemiconductor apparatus according to claim 22, wherein an internalcurrent is determined based on the state of the first terminal.
 29. Thesemiconductor apparatus according to claim 22, wherein an internalthreshold voltage is determined based on the state of the firstterminal.
 30. The semiconductor apparatus according to claim 22, whereinthe detection circuit comprises: a capacitor; a charge circuitstructured to charge the capacitor with a current which is determinedbased on the state of the first terminal; a first comparator structuredto compare a voltage across the capacitor with a first threshold. 31.The semiconductor apparatus according to claim 22, wherein the detectioncircuit comprises a second comparator structured to compare a voltage atthe first terminal with a second threshold.
 32. The semiconductorapparatus according to claim 22, wherein the semiconductor apparatus iscoupled to transmit an assertion of the detection signal with aprimary-side controller so as to instruct the primary-side controller tosuspend a switching operation of a switching transistor.
 33. Thesemiconductor apparatus according to claim 32, further comprising: ashunt regulator output terminal to be coupled connected to an input sideof a feedback photocoupler; and a shunt regulator structured to generatean error current that corresponds to an output voltage of a DC/DCconverter, and to supply an error current to the feedback photocouplerconnected to the shunt regulator output terminal.
 34. The semiconductorapparatus according to claim 33, wherein the semiconductor apparatus iscoupled to transmit an assertion of the detection signal to the primaryside controller via the feedback photocoupler so as to instruct theprimary-side controller to suspend a switching operation of theswitching transistor, and to transmit a feedback signal used in theswitching operation of the switching transistor.
 35. The semiconductorapparatus according to claim 22, further comprising: a fourth terminalto be coupled to an input side of a fail notification photocoupler; anda fail circuit structured to drive the fail notification photocoupler inresponse to an assertion of the detection signal.
 36. The semiconductorapparatus according to claim 35, wherein when the detection signalremains in an asserted state for a predetermined period of time, thefail circuit drives the fail notification photocoupler.